Nonvolatile semiconductor memory devices and voltage control circuit

ABSTRACT

A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2 N  (N=integer) where a reference resistance is indicated by R with the Ns being different from each other; and transistors corresponding to the respective resistance elements, the transistors being controlled by a binary code, and the BCS has a structure obtained by connecting in parallel first structures each constituted by serially connecting a resistance element and the corresponding transistor, and the TCS includes resistance bodies each obtained by connecting in parallel resistance elements with a resistance substantially equal to any of the resistance elements in the BCS; and transistors corresponding to the resistance bodies, controlled by a thermometer code, and the TCS has a structure obtained by connecting in parallel second structures each constituted by serially connecting one of the resistance bodies and the corresponding transistor.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Applications No. 2009-64605, filed on Mar. 17,2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevices and a voltage control circuit, for example, to a NAND flashmemory and to a circuit that controls a write voltage of a NAND flashmemory.

2. Related Art

A voltage generating circuit that generates a write voltage VPGM of aNAND flash memory steps up the write voltage VPGM by a predeterminedstep width ΔVPGM. To reduce the step width ΔVPGM or extend an outputvoltage range of the write voltage VPGM, the number of bits of a digitalsignal for setting the write voltage VPGM needs to be increased.

According to Patent Document 1, a setting circuit receiving athermometer code is constituted by resistance elements (4R) with aresistance ½ of a minimum resistance (for example, 8R) of resistanceelements constituting a setting circuit receiving a binary code. Toincrease the number of bits of a digital signal for setting the writevoltage VPGM in such a voltage setting circuit, low resistance elementsneed to be added to a voltage generating circuit.

For example, to increase the number of bits of the binary code by onebit while keeping the step width ΔVPGM fixed, the resistance element(4R) with a resistance obtained by halving the minimum resistance (8R)before the bit increase is added to the voltage setting circuitreceiving the binary code. In this case, the setting circuit receivingthe thermometer code needs to be constituted by resistance elements (2R)with a resistance obtained by halving the minimum resistance (4R).

As the resistance of the resistance element constituting the voltagesetting circuit is reduced, however, the write voltage VPGM is affectedgreatly. When the resistance values of the resistance elements locallyvary because of variations in manufacturing process or the like,fluctuations in the step width ΔVPGM become larger as the resistancevalues of the resistance elements are smaller. That is, when the numberof bits of the binary code and/or the thermometer code is increased, aprecise control of the step width ΔVPGM becomes difficult. This impedesdownscaling of memory cells and increasing of memory cell values.

SUMMARY OF THE INVENTION

A nonvolatile semiconductor memory device according to an embodiment ofthe present invention comprises: a differential amplifier comprising afirst input receiving a first reference voltage and a second inputreceiving a comparison voltage, the differential amplifier beingconfigured to output a voltage depending on a difference between thereference voltage and the comparison voltage; a booster configured tooutput a boosted voltage; a boost control portion configured to controlthe booster depending on the output voltage of the differentialamplifier; a feedback resistance connected between the booster and thefirst input; and a voltage setting portion connected between the firstinput and a second reference voltage, wherein

the voltage setting portion comprises a binary-code setting portion anda thermometer-code setting portion,

the binary-code setting portion comprises: a plurality of resistanceelements with resistance values of R×2^(N) (N is an integer) where acertain reference resistance is indicated by R with the Ns beingdifferent from each other; and a plurality of transistors correspondingto the respective resistance elements, the transistors being configuredto be controlled by a binary code, and the binary-code setting portionis configured to have a structure obtained by connecting in parallel aplurality of first structures each constituted by serially connectingone of the resistance elements and the corresponding transistor, and

the thermometer-code setting portion comprises: a plurality ofresistance bodies each obtained by connecting in parallel a plurality ofresistance elements with a resistance substantially equal to any of theresistance elements in the binary-code setting portion; and a pluralityof transistors corresponding to the resistance bodies, configured to becontrolled by a thermometer code, and the thermometer-code settingportion is configured to have a structure obtained by connecting inparallel a plurality of second structures each constituted by seriallyconnecting one of the resistance bodies and the correspondingtransistor.

A voltage control circuit according to an embodiment of the presentinvention comprises: a differential amplifier comprising a first inputreceiving a first reference voltage and a second input receiving acomparison voltage, the differential amplifier being configured tooutput a voltage depending on a difference between the reference voltageand the comparison voltage; a booster configured to output a boostedvoltage; a boost control portion configured to control the boosterdepending on the output voltage of the differential amplifier; afeedback resistance connected between the booster and the first input;and a voltage setting portion connected between the first input and asecond reference voltage, wherein

the voltage setting portion comprises a binary-code setting portion anda thermometer-code setting portion,

the binary-code setting portion comprises: a plurality of resistanceelements with resistance values of R×2^(N) (N is an integer) where acertain reference resistance is indicated by R with the Ns beingdifferent from each other; and a plurality of transistors correspondingto the respective resistance elements, the transistors being configuredto be controlled by a binary code, and the binary-code setting portionis configured to have a structure obtained by connecting in parallel aplurality of first structures each constituted by serially connectingone of the resistance elements and the corresponding transistor, and

the thermometer-code setting portion comprises: a plurality ofresistance bodies each obtained by connecting in parallel a plurality ofresistance elements with a resistance substantially equal to any of theresistance elements in the binary-code setting portion; and a pluralityof transistors corresponding to the resistance bodies, configured to becontrolled by a thermometer code, and the thermometer-code settingportion is configured to have a structure obtained by connecting inparallel a plurality of second structures each constituted by seriallyconnecting one of the resistance bodies and the correspondingtransistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of a voltage generating circuit of a NAND flashmemory according to one embodiment of the present invention;

FIG. 2 is a table showing cases 1 to 7 that the step width ΔVPGM variesgreatly;

FIG. 3 is a graph showing a relationship between the binary code, thethermometer code, and the step width ΔVPGM in the voltage controlcircuit disclosed in Patent Document 1;

FIG. 4 is a graph showing a relationship between the binary code, thethermometer code, and the step width ΔVPGM in the voltage controlcircuit according to the present embodiment;

FIGS. 5A˜5C show respectively a structure of a thermometer-code-typeresistance element or a thermometer-code-type resistance body;

FIG. 6 is a graph showing a relationship between the number of thereference resistance elements Rref and the fluctuations in the stepwidth ΔVPGM; and

FIG. 7 is a block diagram showing an example of a NAND flash memory 10including the voltage control circuit of the present embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be explained below in detailwith reference to the accompanying drawings. Note that the invention isnot limited thereto.

FIG. 1 shows an example of a voltage generating circuit of a NAND flashmemory according to one embodiment of the present invention. The voltagegenerating circuit of the present embodiment can be applied to, inaddition to the NAND flash memory, other nonvolatile semiconductormemory devices (hereinafter, simply “memories”).

In the nonvolatile semiconductor memory device, when data is to bewritten in memory cells, a write sequence is repeated by stepping up aword line voltage (also “write voltage” or “program voltage”) so thatthreshold voltages of a large number of memory cells fall within atarget distribution. When the threshold voltages of all selected memorycells are within the target distribution, the write operation iscompleted. Namely, one write operation includes a plurality of writesequences.

In multivalued memories storing plural bits of data in a single memorycell, many levels of the threshold voltage need to be set. For thispurpose, the target distribution of the threshold voltage needs to beset narrow. When the memory cells are downscaled, the threshold voltagesof the memory cells are reduced. Accordingly, also the targetdistribution of the threshold voltage needs to be set narrow. To makethe target distribution of the threshold voltage narrow, a step widthΔVPGM of a write voltage VPGM in each write sequence needs to bereduced. When the step width ΔVPGM is reduced, the number of writesequences repeated in one write operation is increased. Accordingly, thenumber of bits of a binary code and/or a thermometer code is increased.

Downscaling of the multivalued memories and the memory cells can beachieved by extending the range of the write voltage VPGM withoutchanging the step width ΔVPGM. In this case, the range of the writevoltage VPGM is extended and thus the number of write sequences repeatedin one write operation is substantially increased. In both cases, it islikely that the number of bits of the binary code and/or the thermometercode is increased by storing the multivalued data in the memory cell ordownscaling the memory cell.

A voltage control circuit VC according to the present embodiment has aconfiguration shown in FIG. 1 to suppress fluctuations in the step widthΔVPGM even if the number of bits of the binary code and/or thethermometer code is increased. The binary code is a data coderepresenting the write voltage VPGM using a binary number. Thethermometer code is data added to a higher order than the binary codeand is a data code representing the write voltage VPGM using the numberof “1” bits in the binary system.

The voltage control circuit VC according to the present embodimentincludes a boost control circuit 101, a voltage boosting circuit(booster) 102, a differential amplifier AMP, a feedback resistanceelement RL, a minimum-voltage generating circuit 170, and a voltagesetting circuit 100.

The voltage boosting circuit 102 is configured to output a boosted writevoltage VPGM by control of the boost control circuit 101. Thedifferential amplifier AMP includes a first input receiving a firstreference voltage Vref and a second input receiving a monitor voltageVMON serving as a comparison voltage at a node Node. The differentialamplifier AMP outputs a voltage VFLG depending on a difference betweenthe first reference voltage Vref and the monitor voltage VMON. The boostcontrol circuit 101 causes the voltage boosting circuit 102 to perform aboosting operation or stops the boosting operation of the voltageboosting circuit 102 according to the voltage VFLG.

For example, when the monitor voltage VMON is lower than the referencevoltage Vref, the voltage VFLG is a positive voltage. The boost controlcircuit 101 thus causes the voltage boosting circuit 102 to perform theboosting operation, so that the write voltage VPGM is increased.

When the VPGM voltage is increased and the monitor voltage VMON ishigher than the reference voltage Vref, the voltage VFLG is a negativevoltage. The boost control circuit 101 thus stops the boosting operationof the voltage boosting circuit 102.

As described above, the voltage control circuit VC feedbacks the writevoltage VPGM through the feedback resistance element RL to thedifferential amplifier AMP so that the monitor voltage VMON is equal tothe reference voltage Vref. The voltage control circuit VC can thusoutput a stable write voltage VPGM.

The feedback resistance element RL is connected between an output of thevoltage boosting circuit 102 and the node Node. The monitor voltage VMONis obtained by dividing the write voltage VPGM by the feedbackresistance element RL, the minimum-voltage generating circuit 170, andthe voltage setting circuit 100. Assume that a resistance between thenode Node and a ground serving as a second reference voltage (combinedresistance of the minimum-voltage generating circuit 170 and the voltagesetting circuit 100) is indicated by RS. The write voltage VPGM isrepresented by Expression 1.

VPGM=Vref×(1+RL/RS)  (Expression 1)

The minimum-voltage generating circuit 170 includes a gate transistor TMand a resistance RM for setting a minimum value of the write voltageVPGM. During the write operation, the gate transistor TM is always on.When all gate transistors in the voltage setting circuit 100 areswitched off, the write voltage VPGM has a minimum value VPGM_MIN.

VPGM_MIN=Vref×(1+RL/RM)  (Expression 2)

The voltage setting circuit 100 is connected between the node Node andthe ground and includes a binary-code setting portion BCS and athermometer-code setting portion TCS. The voltage setting circuit 100controls a current flowing from a power supply with a voltage equal tothe first reference voltage Vref by selecting resistance elements. Avoltage decrease in the feedback resistance element RL is thuscontrolled and the write voltage VPGM is set.

The binary-code setting portion BCS includes a plurality of resistanceelements 2^(N)R with resistance values of R×2^(N) wherein a referenceresistance is indicated by R and values of N are different from eachother, and a plurality of gate transistors B<0> to B<i> corresponding tothe resistance elements 2^(N)R, respectively, and being controlled by abinary code. N and i are integers. Referring to FIG. 1, the binary-codesetting portion BCS includes resistance elements 4R (N=2), 8R (N=3), 16R(N=4), 32R (N=5), and 64R (N=6). The resistance element 2^(N)R has aresistance value 2^(N) times the reference resistance R.

The binary-code setting portion BCS includes gate transistors B<0>,B<1>, B<2>, B<3>, and B<4>. The gate transistors B<0>, B<1>, B<2>, B<3>,and B<4> correspond to the resistance elements 64R, 32R, 16R, 8R, and4R, respectively.

The resistance elements 64R, 32R, 16R, 8R, and 4R and the correspondinggate transistors B<0>, B<1>, B<2>, B<3>, and B<4> are serially connectedto constitute first structures. For example, the gate transistor B<0>and the resistance element 64R are serially connected to each otherbetween the node Node and the ground to constitute a first structureC10. Similarly, the gate transistor B<i> and the resistance element2^((6−i))R are serially connected to each other between the node Nodeand the ground to constitute the first structure C1 i.

The first structures C10 to C14 are connected to each other in parallelbetween the node Node and the ground. The first structure C10 receives aleast significant bit (LSB) of the binary code. The first structures C11to C13 receive a second bit (second digit), a third bit (third digit),and a fourth bit (fourth digit) of the binary code, respectively. Thefirst structure C14 receives a most significant bit (MSB) of the binarycode.

When a certain bit of the binary code is “0”, the gate transistorcorresponding to that bit is switched off. When a certain bit of thebinary code is “1”, the gate transistor corresponding to that bit isswitched on. For example, when the binary code is “10101”, the gatetransistors B<3> and B<1> are switched off and the gate transistorsB<4>, B<2>, and B<0> are switched on.

The resistance values of the resistance elements are arranged in thebinary-code setting portion BCS so as to be doubled from the mostsignificant bit MSB of the binary code toward the least significant bitLSB thereof, respectively. The binary-code setting portion BCS can thuschange in a stepwise manner (step up) the current according to thebinary code at regular intervals. As a result, the present embodimentcan step up the write voltage VPGM by an equal step width ΔVPGM in astepwise manner.

The step width ΔVPGM is represented by Expression 3.

ΔVPGM=Vref×RL/64R  (Expression 3)

Namely, the step width ΔVPGM depends on the resistance elementcorresponding to the least significant bit LSB of the binary code (64Rin this embodiment). The resistance element 64R has a maximum resistancevalue Rmax with a value of N largest in the binary-code setting portionBCS. Accordingly, the step width ΔVPGM can be represented by Expression4.

ΔVPGM=Vref×RL/Rmax  (Expression 4)

The thermometer-code setting portion TCS includes a plurality ofresistance elements 4R00 to 4R61 with a resistance substantially equalto the resistance of the resistance element 4R which is the lowest inthe binary-code setting portion BCS. The resistance elements 4R00 to4R61 are connected in parallel in pairs to constitute resistance bodiesRB0 to RB6. For example, the resistance elements 4R00 and 4R01 areconnected to each other in parallel to constitute the resistance bodyRB0. Similarly, the resistance elements 4Ri0 and 4Ri1 are connected toeach other in parallel to constitute the resistance body RBi.

The thermometer-code setting portion TCS further includes gatetransistors T<0> to T<6> corresponding to the resistance bodies RB0 toRB6, respectively. The resistance bodies RB0 to RB6 and thecorresponding gate transistors T<0> to T<6> are serially connected toeach other to constitute second structures C20 to C 26, respectively.For example, the gate transistor T<0> and the resistance body RB0 areserially connected to each other between the node Node and the ground toconstitute the second structure C20. Similarly, the gate transistor T<i>and the resistance body RBi are serially connected to each other betweenthe node Node and the ground to constitute the second structure C2 i.

The second structures C20 to C26 are connected to each other in parallelbetween the node Node and the ground. The second structures C20 to C26receive a thermometer code. The thermometer code is a data coderepresenting a value by the number of “1” bits in the binary system. Forexample, decimal numbers “0”, “1”, “2”, “3”, “4”, “5”, “6”, and “7” arerepresented as “000”, “001”, “010”, “011”, “100”, “101”, “110”, and“111” in the binary data, respectively, and as “0000000”, “0000001”,“0000011”, “0000111”, “0001111”, “0011111”, “0111111”, and “1111111” inthermometer code, respectively. Namely, seven bits of the thermometercode correspond to three bits of the binary code.

When a certain bit of the thermometer code is “0”, the gate transistorcorresponding to that bit is switched off. When a certain bit of thethermometer code is “1”, the gate transistor corresponding to that bitis switched on. For example, when the thermometer code is “1010101”, thegate transistors T<5>, T<3>, and T<1> are switched off and the gatetransistors T<6>, T<4>, T<2>, and T<0> are switched on.

As described above, the resistance bodies RB0 to RB6 are configured byconnecting in parallel two resistance elements 4Ri0 and 4R11 with theminimum resistance value in the binary-code setting portion BCS. Theresistance value of the resistance bodies RB0 to RB6 thus becomes ½ ofthe resistance value of the minimum resistance element 4R in thebinary-code setting portion BCS. Because of such configuration,fluctuations in the step width ΔVPGM are decreased. The reason will bedescribed later with reference to FIGS. 5A to 5C.

The binary-code setting portion BCS shown in FIG. 1 can change the writevoltage VPGM with 5 bits in 32 steps. The thermometer-code settingportion TCS can change the write voltage VPGM with 7 bits in 8 steps.One is carried in the thermometer code when the binary code changes from“11111” to “00000”. For example, the thermometer code changes from“0000011” to “0000111”. Accordingly, the voltage setting circuit 100 canchange the write voltage VPGM in 32×8 steps in total

The write voltage VPGM is generalized by Expression 5.

VPGM=VPGM_MIN+ΔVPGM×(32×(T<6>+T<5>+T<4>+T<3>+T<2>+T<1>+T<0>)×16×B<4>+8×B<3>+4×B<2>+2B<1>+B<0>)  (Expression5)

where the gate transistors B<0> to B<4> and T<0> to T<6> are “1” in onstates and “0” in off states.

According to the present embodiment, a current-adding D/A converterusing the combination of the binary code and the thermometer code isutilized as the voltage setting circuit. The binary code is used for thelower bits and the thermometer code is used for the upper bits.

When the entire voltage setting circuit 100 is configured by thebinary-code setting portion BCS, a low resistance element such as thereference resistance R needs to be used to increase the number of digitsof a binary code. As described above, as the resistance of theresistance element is decreased, fluctuations in the step width ΔVPGMare generally increased. Accordingly, the voltage setting circuit 100 ispreferably configured by resistance elements with relatively highresistance values.

The thermometer-code setting portion in Patent Document 1 is configuredusing the resistance elements with a resistance value ½ of theresistance elements 4R having a smallest N in the binary-code settingportion as they are. When the number of digits of the binary code isincreased while maintaining the step width ΔVPGM (while keeping 64R theleast significant bit, for example), the resistance values of theresistance elements constituting the thermometer-code setting portionTCS need to be reduced. In this case, when the binary code changes from“11111” to “00000”, that is, when one is carried in the thermometer codeas shown in FIG. 2, the step width ΔVPGM fluctuates greatly.

FIG. 2 is a table showing cases 1 to 7 that the step width ΔVPGM variesgreatly. For example, according to the case 1, the thermometer codechanges from “0000000” to “0000001” when the binary code changes from“11111” to “00000”. Similarly, in the case i, the ith bit of thethermometer code is changed from 0 to 1 when the binary code changesfrom “11111” to “00000”. The step width ΔVPGM fluctuates greatly in thecases 1 to 7.

FIG. 3 is a graph showing a relationship between the binary code, thethermometer code, and the step width ΔVPGM in the voltage controlcircuit disclosed in Patent Document 1. A horizontal axis VPGM_DACindicates values representing the binary code and the thermometer codeby hexadecimal numbers. “1F” of VPGM_DAC corresponds to the case 1 shownin FIG. 2. “3F” of VPGM_DAC corresponds to the case 2 shown in FIG. 2.“5F” of VPGM_DAC corresponds to the case 3 shown in FIG. 2. It can beunderstood that fluctuations in the step width ΔVPGM are large whenVPGM_DAC is “1F”, “3F”, and “5F”.

FIG. 4 is a graph showing a relationship between the binary code, thethermometer code, and the step width ΔVPGM in the voltage controlcircuit according to the present embodiment. It can be clearlyunderstood that fluctuations in the step width ΔVPGM are reduced whenVPGM_DAC is “1F”, “3F”, and “5F”. The reason why the fluctuations in thestep width ΔVPGM are reduced is as follows.

In the present embodiment, the thermometer-code-type resistance bodiesRB0 to RB6 are configured by connecting in parallel two resistanceelements 4R with the minimum resistance value, which is the binary codetype's most significant bit MSB. The resistance element is usuallyconfigured by serially connecting the reference resistance elements Rrefwith the reference resistance R as shown in FIG. 5A. For example, theresistance element 4R with a resistance of R×4 is configured by seriallyconnecting four reference resistance elements. As shown in FIG. 5C, eachof the thermometer-code-type resistance bodies RB0 to RB6 is configuredby eight reference resistance elements in the present embodiment. Forexample, the reference resistance element is made of doped polysiliconor a diffusion layer. The doped polysilicon can be the one on the samelayer as a floating gate of the memory cell.

On the other hand, the thermometer-code-type resistance element inPatent Document 1 is configured by the resistance element 2R having theresistance value ½ of the minimum resistance value which is the binarycode type's most significant bit MSB. As shown in FIG. 5B, thethermometer code type resistance element in Patent Document 1 isconfigured by two reference resistance elements to realize theresistance value of 2R.

FIG. 6 is a graph showing a relationship between the number of thereference resistance elements Rref and the fluctuations in the stepwidth ΔVPGM. When the binary code (B<0>, B<1>, B<2>, B<3>) changes from(0, 0, 0, 1) to (0, 0, 1, 0), differences ( 1/32R−− 1/64R) betweenreciprocals of resistance values in the binary-code setting portion BCSare distributed as shown by a curve A. When the binary code (B<0>, B<1>,B<2>, B<3>) changes from (0, 0, 1, 1) to (0, 1, 0, 0), differences (1/16R− 1/32R− 1/64R) between the reciprocals of the resistance values inthe binary-code setting portion BCS are distributed as shown by a curveB. When the binary code (B<0>, B<1>, B<2>, B<3>) changes from (0, 1,1, 1) to (1, 0, 0, 0), differences (⅛R− 1/16R− 1/32R− 1/64R) between thereciprocals of the resistance values in the binary-code setting portionBCS are distributed as shown by a curve C.

Assume that the voltage VMON between the node Node and the ground isfixed. The difference between the reciprocals of the resistance valuesin the binary-code setting portion is proportional to a differencebetween currents flowing in the binary-code setting portion. The curvesA to C are thus similar to the distribution of fluctuations in the stepwidth ΔVPGM when the binary code changes as described above.

Ideally, the reciprocal of the resistance value in the binary-codesetting portion BCS should be increased equally by 1/64R every time whenone is carried in the binary code. Namely, the write voltage VPGM shouldbe ideally increased by a fixed step width ΔVPGM every time when one iscarried in the binary code.

The resistance value R of the reference resistance element, however,fluctuates to a certain extent. When the number of reference resistanceelements is reduced because of the carry in the binary code like in thecurves A to C, an error in the reciprocal of the resistance value in thebinary-code setting portion BCS is increased. For example, the number ofreference resistance elements changes from eight to four in the curve A(when the binary code changes from (0, 0, 0, 1) to (0, 0, 1, 0)). Thenumber of reference resistance elements changes from twelve to two inthe curve B (when the binary code changes from (0, 0, 1, 1) to (0, 1, 0,0)). The number of reference resistance elements changes from fourteento one in the curve C (when the binary code changes from (0, 1, 1, 1) to(1, 0, 0, 0)). Namely, the rate of decrease in the number of referenceresistance elements is the largest in the curve C and becomes smaller inthe order of B, A. Correspondingly, the fluctuations in the step widthΔVPGM are the largest in the curve C and become smaller in the order ofB, A.

It can be understood from the graph that when the rate of decrease inthe number of reference resistance elements is reduced, the fluctuationsin the step width ΔVPGM are also reduced. The rate of decrease in thenumber of reference resistance elements can be calculated by (Nb−Na)/Nbwhere the number of reference resistance elements connected between thenode Node and the ground before the binary code is changed is indicatedby Nb and the number of reference resistance elements connected betweenthe node Node and the ground after the binary code is changed isindicated by Na.

Because the resistance body RBi in the thermometer-code setting portionTCS is constituted by the plural resistance elements R4 connected toeach other in parallel in the voltage control circuit according to thepresent embodiment, the rate of decrease in the number of referenceresistance elements becomes smaller when a digit is carried from thebinary-code setting portion BCS to the thermometer-code setting portionTCS as compared to the conventional case. As a result, the fluctuationsin the step width ΔVPGM can be reduced in the voltage control circuitaccording to the present embodiment.

As the number of reference resistance elements Rref is increased, thearea of the thermometer-code setting portion TCS is increased. When thethermometer-code setting portion TCS according to the present embodimentis used, however, a precise control of the write voltage VPGM requiredto downscale the memory cells can be realized. Because an increase inthe chip size in the present embodiment is negligibly small, the chipsize is little affected. Even if the chip size of the present embodimentis not reduced, a different effect that the fluctuations in the stepwidth ΔVPGM are reduced can be obtained.

Persons skilled in the art usually intend to make the resistance elementof the thermometer-code setting portion TCS smaller (lesser) to reducethe chip size. The present inventors, however, found that by daringlyincreasing the number of reference resistance elements Rref constitutingthe thermometer-code setting portion TCS, the fluctuations in the stepwidth ΔVPGM can be suppressed.

To obtain the resistance value of 2R, two resistance elements 4R areconnected in parallel in the present embodiment. More referenceresistance elements Rref can be used to obtain the resistance value of2R. For example, four resistance elements with a resistance value of 8Rin the binary-code setting portion BCS can be connected in parallel.Further, n/2 resistance elements with a resistance value of nR can beconnected in parallel. In other words, while the thermometer-codesetting portion TCS is constituted by resistance elements Rmin with thelowest resistance value in the binary-code setting portion BCS in thepresent embodiment, the thermometer-code setting portion TCS can bealternatively constituted by the resistance elements Rk with the kth (kis an integer) lowest resistance value in the binary-code settingportion BCS. In this case, the resistance body constituting thethermometer-code setting portion TCS can be configured by 2^(k)resistance elements. Rk indicates a resistance element with the kthlowest resistance value in the binary-code setting portion BCS or aresistance value thereof. Rmin indicates a resistance element with thelowest resistance value in the binary-code setting portion BCS or aresistance value thereof.

According to the present embodiment, even if the resistance value of thethermometer-code setting portion TCS is substantially decreased toreduce the step width ΔVPGM of the output voltage or to extend the rangeof the write voltage VPGM, the fluctuations in the step width ΔVPGM canbe suppressed.

FIG. 7 is a block diagram showing an example of a NAND flash memory 10(hereinafter, simply “the memory 10”) including the voltage controlcircuit of the present embodiment. The memory 10 includes a memory cellarray MCA, a row decoder RD, a column decoder CD, a sense amplifier S/A,an input/output buffer IOB, a voltage generating circuit VG, an externalI/O pad IOP, a bit line hookup BLH, a word line hookup WLH, a commanddecoder CMD, and an address buffer ADDB.

Write data, an address, and a command are inputted via the external I/Opad IOP to the input/output buffer IOB. Read data is outputted from theinput/output buffer IOB via the external I/O pad IOP. The input/outputbuffer IOB transmits the command to the command decoder CMD, the addressto the row decoder RD and the column decoder CD, and the data to a datalatch in the sense amplifier S/A. The row decoder RD decodes the addressand selects a word line based on an address signal. The column decoderCD decodes the address, selects a sense amplifier in the sense amplifierS/A based on the address signal, and transfers the read data latched bythe selected sense amplifier to a data bus or the externally receivedwrite data to the selected sense amplifier. The sense amplifier S/Aconsists of a plurality of sense amplifiers corresponding to therespective bit lines. The configuration of the sense amplifier S/A canbe an already known one.

The voltage generating circuit VG receives a voltage level settingsignal to generate internal voltages such as a reference voltage Vreffor reference, an internal step-down supply voltage VDD, and a writevoltage VPGM from an externally supplied supply voltage VCC. The voltagegenerating circuit VG supplies the internal voltages to the row decoderRD, the column decoder CD, the sense amplifier S/A, and a cell sourcedriver CSD. The voltage control circuit VC according to the presentembodiment is provided in the voltage generating circuit VG.

The word line hookup WLH applies the write voltage VPGM from the voltagegenerating circuit VG to a selected word line. To change the selectedword line, the word line hookup WLH changes connection between the wordline WL and the row decoder RD. Thus, voltage control circuit VCaccording to the present embodiment can be applied to the NAND flashmemory.

1. A nonvolatile semiconductor memory device comprising: a differentialamplifier comprising a first input receiving a first reference voltageand a second input receiving a comparison voltage, the differentialamplifier being configured to output a voltage depending on a differencebetween the reference voltage and the comparison voltage; a boosterconfigured to output a boosted voltage; a boost control portionconfigured to control the booster depending on the output voltage of thedifferential amplifier; a feedback resistance connected between thebooster and the first input; and a voltage setting portion connectedbetween the first input and a second reference voltage, wherein thevoltage setting portion comprises a binary-code setting portion and athermometer-code setting portion, the binary-code setting portioncomprises: a plurality of resistance elements with resistance values ofR×2^(N) (N is an integer) where a certain reference resistance isindicated by R with the Ns being different from each other; and aplurality of transistors corresponding to the respective resistanceelements, the transistors being configured to be controlled by a binarycode, and the binary-code setting portion is configured to have astructure obtained by connecting in parallel a plurality of firststructures each constituted by serially connecting one of the resistanceelements and the corresponding transistor, and the thermometer-codesetting portion comprises: a plurality of resistance bodies eachobtained by connecting in parallel a plurality of resistance elementswith a resistance substantially equal to any of the resistance elementsin the binary-code setting portion; and a plurality of transistorscorresponding to the resistance bodies, configured to be controlled by athermometer code, and the thermometer-code setting portion is configuredto have a structure obtained by connecting in parallel a plurality ofsecond structures each constituted by serially connecting one of theresistance bodies and the corresponding transistor.
 2. The device ofclaim 1, wherein the binary-code setting portion is configured to flow acurrent through the resistance element connected to at least one of thetransistors selected according to the binary code so as to control acurrent flowing through the feedback resistance and set the voltageoutputted from the booster in a stepwise manner, and thethermometer-code setting portion is configured to flow a current throughthe resistance body connected to at least one of the transistorsselected according to the thermometer code so as to control the currentflowing through the feedback resistance and set the voltage outputtedfrom the booster in a stepwise manner.
 3. The device of claim 2, whereineach of the resistance bodies is constituted by connecting in paralleltwo resistance elements with a resistance substantially equal to that ofa resistance element with a smallest one of the Ns in the binary-codesetting portion.
 4. The device of claim 2, wherein when the voltageoutputted from the booster is indicated by VPGM, the first referencevoltage is indicated by Vref, a resistance value of the feedbackresistance is indicated by RL, and a resistance value of a resistanceelement with a largest one of the Ns in the binary-code setting portionis indicated by Rmax, a step width ΔVPGM of the VPGM is represented byΔVPGM=Vref×(RL/Rmax).
 5. The device of claim 3, wherein when the voltageoutputted from the booster is indicated by VPGM, the first referencevoltage is indicated by Vref, a resistance value of the feedbackresistance is indicated by RL, and a resistance value of a resistanceelement with a largest one of the Ns in the binary-code setting portionis indicated by Rmax, a step width ΔVPGM of the VPGM is represented byΔVPGM=Vref×(RL/Rmax).
 6. The device of claim 2, wherein the resistanceelements in the binary-code setting portion have resistance valuesR×2^(k) (k is an integer), R×2^(k−1), R×2^(k−2), R×2^(k−3), onwardscorresponding to respective bits from a lower one to an upper one of thebinary code.
 7. The device of claim 3, wherein the resistance elementsin the binary-code setting portion have resistance values R×2^(k) (k isan integer), R×2^(k−1), R×2^(k−2), R×2^(k−3), onwards corresponding torespective bits from a lower one to an upper one of the binary code. 8.The device of claim 4, wherein the resistance elements in thebinary-code setting portion have resistance values R×2^(k) (k is aninteger), R×2^(k−1), R×2^(k−2), R×2^(k−3), onwards corresponding torespective bits from a lower one to an upper one of the binary code. 9.The device of claim 2, wherein the N of the resistance elementcorresponding to a least significant bit of the binary code is largestamong the resistance elements in the binary-code setting portion, andthe N of the resistance element corresponding to a most significant bitof the binary code is smallest among the resistance elements in thebinary-code setting portion.
 10. The device of claim 3, wherein the N ofthe resistance element corresponding to a least significant bit of thebinary code is largest among the resistance elements in the binary-codesetting portion, and the N of the resistance element corresponding to amost significant bit of the binary code is smallest among the resistanceelements in the binary-code setting portion.
 11. The device of claim 4,wherein the N of the resistance element corresponding to a leastsignificant bit of the binary code is largest among the resistanceelements in the binary-code setting portion, and the N of the resistanceelement corresponding to a most significant bit of the binary code issmallest among the resistance elements in the binary-code settingportion.
 12. The device of claim 5, wherein the N of the resistanceelement corresponding to a least significant bit of the binary code islargest among the resistance elements in the binary-code settingportion, and the N of the resistance element corresponding to a mostsignificant bit of the binary code is smallest among the resistanceelements in the binary-code setting portion.
 13. The device of claim 4,wherein the voltage setting portion increases the VPGM from apredetermined minimum value by the step width ΔVPGM.
 14. The device ofclaim 5, wherein the voltage setting portion increases the VPGM from apredetermined minimum value by the step width ΔVPGM.
 15. The device ofclaim 4, wherein the VPGM is a write voltage of a NAND flash memory. 16.The device of claim 13, wherein the VPGM is a write voltage of a NANDflash memory.
 17. A voltage control circuit comprising: a differentialamplifier comprising a first input receiving a first reference voltageand a second input receiving a comparison voltage, the differentialamplifier being configured to output a voltage depending on a differencebetween the reference voltage and the comparison voltage; a boosterconfigured to output a boosted voltage; a boost control portionconfigured to control the booster depending on the output voltage of thedifferential amplifier; a feedback resistance connected between thebooster and the first input; and a voltage setting portion connectedbetween the first input and a second reference voltage, wherein thevoltage setting portion comprises a binary-code setting portion and athermometer-code setting portion, the binary-code setting portioncomprises: a plurality of resistance elements with resistance values ofR×2^(N) (N is an integer) where a certain reference resistance isindicated by R with the Ns being different from each other; and aplurality of transistors corresponding to the respective resistanceelements, the transistors being configured to be controlled by a binarycode, and the binary-code setting portion is configured to have astructure obtained by connecting in parallel a plurality of firststructures each constituted by serially connecting one of the resistanceelements and the corresponding transistor, and the thermometer-codesetting portion comprises: a plurality of resistance bodies eachobtained by connecting in parallel a plurality of resistance elementswith a resistance substantially equal to any of the resistance elementsin the binary-code setting portion; and a plurality of transistorscorresponding to the resistance bodies, configured to be controlled by athermometer code, and the thermometer-code setting portion is configuredto have a structure obtained by connecting in parallel a plurality ofsecond structures each constituted by serially connecting one of theresistance bodies and the corresponding transistor.
 18. The circuit ofclaim 17, wherein the binary-code setting portion is configured to flowa current through the resistance element connected to at least one ofthe transistors selected according to the binary code so as to control acurrent flowing through the feedback resistance and set the voltageoutputted from the booster in a stepwise manner, and thethermometer-code setting portion is configured to flow a current throughthe resistance body connected to at least one of the transistorsselected according to the thermometer code so as to control the currentflowing through the feedback resistance and set the voltage outputtedfrom the booster in a stepwise manner.